AND combine with OR

AND combine with OR 

module top; 

wire A, B, C, D,OUT1, OUT2,OUT3;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

and a1(OUT1, A, B);

and a2(OUT2, C, D);

or a3(OUT3, OUT2, OUT1);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

心得:

這次是加分題 與同學競爭 寫出這題 最後幸運的加到分很

爽 哈哈 !!